• Senior Engineer, Packaging Engineering

• Taichung |    Jan 23, 2018 Western Digital
• Western Digital - Taichung City - Western Digital We deliver the possibilities of data. YOU define what's possible. Optimize flip chip bump pad, die bonding pad and s...
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• Staff Engineer, Electronic Design Engineering

• Taipei City |    Dec 17, 2017 Western Digital
• Western Digital - Taipei City - Responsibilities include: o Writing Technical Specifications for their designs as well as for the designs that we need our ODM partners
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• Staff Engineer, Hw Design

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - Do you have a passion working on leading edge technology? Are you passionate about working closely with next generation enterprise SSDs...
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• Principal Engr, Asic Design Verification

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Job Description: Job Description Looking for ASIC Verification Engineer, responsible for. Development of ASIC verification and
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• Principal Engr, Asic Design Verification

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Looking for ASIC Verification Engineer, responsible for: Development of ASIC verification and Validation plans Development of UVM
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• Principal Engineer Fpga Rtl Design

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - FPGA Platforms Job description 1.Xilinx FPGA development experience. Virtex 7 FPGA preferred 2.Vivado tool experience 3.Able to ve...
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• Principal Engineer Fpga Rtl Design

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - 4.Experience with design timing constraints, timing closure and static timing analysis 5.Experience with FPGA floor planning tool 6
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• Principal Engineer, Asic Development Engineering

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Work with architecture team to define SOC micro architecture design specification, IP specification, implement new IP or customize
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• Principal Engineer, Asic Development Engineering

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - Work with architecture team to define SOC micro architecture design specification, IP specification, implement new IP or customize
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• Senior Engineer, Packaging Engineering

• Taichung |    Dec 29, 2017 Western Digital
• Western Digital - Taichung City - Optimize die bonding pad and substrate(BGA, LGA, SIP)/ PCB layouts for possible design simplification and cost reduction of Multi-Chip
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• Principle Engineer

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - The new hire engineer will be accountable and responsible for the eSSD package designs. Working with ASIC vendors and internal teams
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• Staff Engineer, Asic Development Engineering

• Hsinchu |    Dec 26, 2017 Western Digital
• Western Digital - Hsinchu County - 1. Design quality check and IP deliverables check in early stage (Lint, CDC, synthesis, STA, formal check, database integrity check)2
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• Principle Engineer

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Job Description Summary The new hire engineer will be accountable and responsible for the eSSD package designs. Working with ASIC
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• Staff Engineer, Packaging Engineering

• Taichung |    Dec 19, 2017 Western Digital
• Western Digital - Taichung City - Western Digital We deliver the possibilities of data. YOU define what's possible. Optimize flip chip bump pad, die bonding pad and s...
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