• Asic Design Verification Engineer

• Hsinchu |    Jan 10, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Asic Design Verification Engineer

• Hsinchu |    Jan 7, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engineer, Asic Development Engineering

• Hsinchu |    Feb 4, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Asic Design Verification Engineer

• Hsinchu |    Jan 3, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Asic Design Verification Engineer

• Hsinchu |    Jan 2, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Asic Design Verification Engineer

• Hsinchu |    Dec 31, 2017 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Staff Engineer, Asic Development Engineering

• Hsinchu |    Jan 26, 2018 Western Digital
• Western Digital - Hsinchu County - Essential Duties and responsibilities:Definition and design of test-bench and test plan for verifying Chip Level RTLDevelop complex
  Share |  Save this job
  Share this job on -

  [x]

• Staff Engineer, Hw Design

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - Do you have a passion working on leading edge technology? Are you passionate about working closely with next generation enterprise SSDs...
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engr, Asic Design Verification

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Job Description: Job Description Looking for ASIC Verification Engineer, responsible for. Development of ASIC verification and
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engr, Asic Design Verification

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Looking for ASIC Verification Engineer, responsible for: Development of ASIC verification and Validation plans Development of UVM
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engineer Fpga Rtl Design

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - FPGA Platforms Job description 1.Xilinx FPGA development experience. Virtex 7 FPGA preferred 2.Vivado tool experience 3.Able to ve...
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engineer Fpga Rtl Design

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - 4.Experience with design timing constraints, timing closure and static timing analysis 5.Experience with FPGA floor planning tool 6
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engineer, Asic Development Engineering

• Hsinchu |    Dec 17, 2017 Western Digital
• Western Digital - Hsinchu County - Work with architecture team to define SOC micro architecture design specification, IP specification, implement new IP or customize
  Share |  Save this job
  Share this job on -

  [x]

• Principal Engineer, Asic Development Engineering

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - Work with architecture team to define SOC micro architecture design specification, IP specification, implement new IP or customize
  Share |  Save this job
  Share this job on -

  [x]

• Principle Engineer

• Hsinchu |    Dec 15, 2017 Western Digital
• Western Digital - Hsinchu County - The new hire engineer will be accountable and responsible for the eSSD package designs. Working with ASIC vendors and internal teams
  Share |  Save this job
  Share this job on -

  [x]